A storage controller in a storage module that contains a plurality of memory dies (e.g., in a multi-die package) needs to know the ready/busy status of the memory dies in order to know when it can send a command to a given memory die. In many storage bus architectures, there is only one ready/busy line, which is shared among all of the memory dies. As such, the storage controller may need to poll each memory die individually for its ready/busy status by continuously changing the die number and issuing a check status command. This approach involves a lot of firmware activity in the controller and requires a lot of power to the controller and bus. Also, there is latency in the time a memory die completes an activity to the time the firmware in the storage controller realizes that the memory die has become ready. Accordingly, determining ready/busy status by polling the memory dies often results in power and performance disadvantages. Instead of polling the memory dies, the storage controller can use a series of timers to estimate when a given memory die will complete an operation and become ready. However, this approach adds complexity to the storage controller and may not provide a true indication of readiness, especially when a memory die takes more time than expected to complete an operation. Another approach uses pulse code modulation of a ready/busy signal; however, collisions can be a problem in that approach.